The present invention relates to an extremely compact, high speed, and high impedance MOS transistor which can be used, for instance, as a high density and high speed switching circuit in a ULSI, SRAM or DRAM.
In the production of switching transistors, how a compact and high speed switching transistor with a low power consumption can be made is one of the most important challenges. In a MOS type FET, the gate length determines the processing speed. How to control the channel resistance and a gate capacity is a challenge in the technological field. On the other hand, when the gate length is extremely short, the so-called short channel effect occurs in which a depletion layer spans out from the drain and gets integrated with a depletion layer in the source side and causes punch-through. Therefore, it has been extremely difficult to shorten the gate length to 0.1 xcexcm or less.
Conventionally various efforts to mitigate the short channel effect have been made. One such design is disclosed in U.S. Pat. No. 4,644,386 wherein a double drain structure or LDD structure on a MIS (MOS) type FET is formed by forming an insulating thin oxide film on a semiconductor surface between a source S and a drain D and forming a gate metal G thereover to further shorten the insulating gate length. However, the channel area has higher resistivity (low density of impurities) and still exhibits problems caused by the short channel effect.
In U.S. Pat. No. 5,177,568, a tunnel transistor has been proposed having a structure similar to that of the MOSFET in which the source and drain are made from metal, the drain is used as an ohmic electrode, a Schottky junction between the source and the semiconductor is used as a tunnel junction, and a tunnel current is controlled by adjusting a MOS gate voltage.
However, the channel area of this structure still exhibits high resistivity (low density of impurities) and the channel area cannot be set in a low resistance state unless a voltage is applied to the MOS gate metal. Because of this, carrier tunneling rarely occurs through the Schottky junction, the threshold voltage is large, the drain area is required to overlap the gate metal, or height of a barrier of the Schottky junction does not change much upon applying a voltage to the MOS gate. Hence, the mutual conductance (Gm) does not become substantially large.
In U.S. Pat. No. 5,552,622, the present applicant invented a tunnel transistor in which a MOS gate is attached to a junction section of a Schottky junction tunnel diode. However, only a barrier of the Schottky junction was used, so that it is difficult to obtain large mutual conductance (Gm). In Japanese Patent Laid-open Publication No. HEI 9-223795), the present applicant also invented a MOS gate Schottky barrier transistor based on a structure in which height of a barrier of the Schottky junction can be effectively changed according to a voltage applied to the MOS gate not only by using a barrier of the Schottky junction, but also by using a high resistivity material for the Schottky metal 7, or by forming a denatured layer on the Schottky junction interface.
With the above invention, emphasis is especially put on the treatment of a carrier flowing over a barrier of the Schottky junction such that a relatively large mutual conductance (Gm) can be realized. However, the disadvantage is that when the transistor is used as a switching transistor and is turned ON, the resistance is higher, and it is difficult to pass a large current at a high speed through the transistor.
It is an object of the present invention to provide a high efficiency switching transistor which is substantially free from the short channel effect, has a simple construction which can be formed into an extremely small size, has a high processing speed as well as high input impedance, has a low power consumption and has a high mutual conductance (Gm) when turned ON and can also be integrated into a high density integrated circuit.
To achieve the object described above, the MOS gate Schottky tunnel transistor according to the present invention is obtained by making use of the fact that, in the MOS gate Schottky tunnel transistor based on a construction shown in FIG. 1 in which the gate metal 3 is provided via an insulating thin film on the Schottky junction having the Schottky metal 7 as the source 2, when a surface area of a first semiconductor layer 8 having, for instance, n-type impurities added, a tunnel junction 5 is formed between the Schottky metal 7 and the first semiconductor layer 8. As a result, the tunnel conductance becomes very large. However, when an extremely thin p-type high density impurities layer, second semiconductor layer 9 is formed between the Schottky metal 7 and the first semiconductor layer 8, a barrier 6 against a tunnel junction, as illustrated in FIG. 5A1, is formed between the Schottky metal 7 and the first semiconductor layer 8. As a result, the tunneling of a carrier current hardly occurs because the current flowing between the source 2 and drain 4 (drain current) becomes very small. In the MOS gate Schottky tunnel transistor according to the present invention, when the height of the barrier 6 against a tunnel junction by second semiconductor layer 9 is lowered by applying a gate voltage, a carrier current comprising a tunnel current passing through the tunnel and a carrier current flowing over barrier 6 (seemingly a hysteric current) is obtained, so that a large drain current can be obtained. Because of this feature, the transistors can be formed into an integrated circuit.
The MOS gate Schottky transistor of this invention can also be regarded as a MOS gate Schottky barrier transistor in which the denatured layer is thin enough for electrons to pass therethrough. The gate metal 3 is provided via an insulating thin film on the Schottky junction. By forming such a denatured layer near a Schottky junction section at least just below the MOS gate, the voltage in the Schottky barrier near the MOS interface can be lowered and a carrier current can move over the Schottky barrier when a voltage is applied to the gate to form a high density carrier accumulation layer in both the Schottky metal just below the MOS gate and the semiconductor portion. A main portion of the current passing through the Schottky junction comprises a carrier current moving over the Schottky barrier according to claim 4 in Japanese patent Laid-open Publication No. HEI 9-223795 filed by this applicant.
A more detailed description of the invention is set forth below. Since in the ordinary Schottky junction, the electric resistance of the Schottky metal 7 is small when a substantial zero bias or a reverse-directional bias is applied to the Schottky junction. Even if a voltage is applied to the Schottky junction, a voltage drop hardly occurs in the side of Schottky metal 7, so that height of the Schottky barrier hardly changes.
Thus, even if a gate voltage is loaded, a change of height of the Schottky barrier cannot be controlled, and the height of the thickness of the Schottky barrier is kept large. Only when the thickness of the Schottky barrier is changed, so that a flow of a carrier current flowing over the Schottky barrier which is thermally excited (a diffusion current) is quite small, can a very small tunnel current with small tunneling probability be obtained. Therefore, it is extremely difficult to make a MOS gate Schottky barrier transistor having a large mutual conductance.
However, with the MOS gate Schottky tunnel transistor according to the present invention, a p-type high density impurities layer (second semiconductor layer 9) is formed near the Schottky junction at least just below the MOS gate such that when a positive voltage is applied to the gate metal 3 to form a further higher density carrier accumulation layer in the semiconductor layer (first semiconductor layer 8), the height of the barrier 6 of the MOS interface on the thin p-type high density impurities layer (second semiconductor layer 9) near the Schottky junction interface becomes lower and also the thickness becomes smaller. Hence, a quantity of a current obtained by summing a carrier passing through the barrier 6 (in this case, electrons and a tunnel carrier also including thermal field emission) and a carrier flowing over the barrier 6 (also in this case, electrons) is substantially increased. Therefore, a MOS gate Schottky tunnel transistor providing large mutual conductance (Gm) can be obtained.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.